Clock synchronizer with offset prevention function against variation of output potential of loop filter

ABSTRACT

A change pump circuit included in a clock synchronizer is capable of preventing occurrence of an offset even though an output potential of a loop filter is varied, and includes a control circuit controlling a gate potential of a transistor such that predetermined constant current flows through the transistor connected between the line of a power-supply potential and an output node of the loop filter by a switching circuit, based on the output potential of the loop filter.

TECHNICAL FIELD

The present invention relates to a clock synchronizer, and particularly,to a clock synchronizer generating a second clock signal synchronizedwith a first clock signal.

BACKGROUND ART

Conventionally, a semiconductor integrated circuit device is providedwith a PLL (Phase Locked Loop) circuit generating an internal clocksignal in synchronization with an external clock signal in order tosynchronize the outside and the inside of a chip.

FIG. 23 is a circuit block diagram showing the configuration of such aPLL circuit. In FIG. 23, the PLL circuit includes a phase comparator121, a charge pump circuit 122, a loop filter 127, a voltage controloscillator (hereinafter referred to as VCO) 130, and a frequency divider131.

An external clock signal is input into phase comparator 121 as areference clock signal RCLK. Phase comparator 121 compares the phase ofreference clock signal RCLK and that of a feedback clock signal FCLK,and outputs signals UP, DOWN based on the comparison result. When thephase of clock signal FCLK is advanced with respect to the phase ofreference clock signal RCLK, signal DOWN is raised to an activated levelof “H” level for a time period corresponding to a phase difference, andwhen the phase of clock signal FCLK is delayed with respect to the phaseof reference clock signal RCLK, signal UP is lowered to an activatedlevel of “L” level for a time period corresponding to a phasedifference. When there is no difference in the phases of clock signalsFCLK and RCLK, signals DOWN, UP are set to be at “H” level and “L”level, respectively, in a pulsive manner.

Charge pump circuit 122 includes a P-channel MOS transistor 123 and aswitching element 124 connected in series between the line of apower-supply potential VCC and a node N122; and a switching element 125and an N-channel MOS transistor 126 connected in series between nodeN122 and the line of a ground potential GND.

The gate of P-channel MOS transistor 123 is supplied with a constantbias potential VBP, whereas the gate of N-channel MOS transistor 126 issupplied with a constant bias potential VBN. Each of MOS transistors123, 126 constitutes a constant-current source. Switching element 124conducts for a period during which signal UP is at the activated levelof “L” level. Switching element 125 conducts for a period during whichsignal DOWN is at the activated level of “H” level.

Loop filter 127 includes a resistance element 128 and a capacitor 129connected in series between node N122 and ground potential GND.Capacitor 129 is charged and discharged by charge pump circuit 122. Thevoltage of node N122 is supplied to VCO 130 as a control voltage VC.

VCO 130 outputs an internal dock signal CLK having a frequencycorresponding to control voltage VC. Internal clock signal CLK isapplied to an internal circuit of the semiconductor integrated circuitdevice and also to frequency divider 131. Frequency divider 131 dividesthe frequency of clock signal CLK by N (wherein N is a positive integer)to generate clock signal FCLK. Clock signal FCLK is returned to phasecomparator 121.

Control voltage VC is adjusted such that the frequencies and phases ofclock signals RCLK and FCLK agree with each other, and then thefrequencies and phases of clock signals RCLK and FCLK agree with eachother, resulting in a lock state. In the locked state, internal clocksignal CLK has a frequency N times as high as that of external clocksignal RCLK and is a signal synchronizing with external clock signalRCLK. The internal circuit of the semiconductor integrated circuitdevice operates in synchronization with internal clock signal CLK.Therefore, the outside and the inside of the chip can be synchronized.

However, the conventional PLL circuit had problems as described below.

Now, a case is considered where reference clock signal RCLK and feedbackclock signal FCLK agree in phase. In this case, signal UP is lowered to“L” level in a pulsive manner for a certain period of time with the samecycle as that of dock signals RCLK, FCLK. Likewise, signal DOWN israised to “H” level in a pulsive manner for the same period of time andwith the same cycle as that of signal UP. The reason why signals UP,DOWN are set to be at “L” level and “H” level in a pulsive manner eventhough clock signals RCLK and FCLK agree in phase with each other is toavoid a dead band being created.

At this moment, if current Ic flowing through P-channel MOS transistor123 is the same as current Id flowing through N-channel MOS transistor126, signals UP and DOWN will have the same pulse width, so that theexactly same amount of charge is charged and discharged without theamount of charge in capacitor 129 of loop filter 127 changed. Thus, nochange occurs in control voltage VC, and VCO 130 keeps outputting clocksignal CLK having the same frequency X (Hz). As a result, the PLLcircuit will be in the locked state in a state having no phasedifference between clock signals RCLK and FCLK.

However, when there is no agreement between charging current Ic anddischarging current Id, the locked state cannot be obtained in the statehaving no phase difference between clock signals RCLK and FCLK. Forexample, considering the case where charging current Ic is larger thandischarging current Id, if signals UP and DOWN have the same pulsewidth, the amount of charge that is charged by charging current Ic willbe unequal to the amount of charge that is discharged by dischargingcurrent Id. To equalize these amount of charges, the pulse width ofsignal DOWN must be made larger than the pulse width of signal UP.

Then, the state where the pulse width of signal DOWN is larger than thepulse width of signal UP means a state where the phase of feedback clocksignal FCLK is delayed with respect to the phase of reference clocksignal RCLK, and the PLL circuit is locked in this state. This generatesa steady phase difference, i.e. an offset, between clock signals RCLKand FCLK. Same applies to the case where discharging current Id islarger than charging current Ic. In sum, in the PLL circuit, if there isno agreement in magnitude between charging current Ic and dischargingcurrent Id, an offset will occur.

Next, a case is considered where charging current Ic and dischargingcurrent Id disagree with each other in magnitude. In designing of thePLL circuit, assuming that the operating frequency of the PLL circuit isX (Hz), VCO 130 obtains a control voltage Y (V) oscillated at X (Hz),and the sizes of MOS transistors 123, 126 and the levels of biaspotentials VBP, VBN are determined such that charging current Ic anddischarging current Id are equal to each other when control voltage VCis Y (V). Therefore, when the PLL circuit operates as designed, chargingcurrent Ic and discharging current Id are equal to each other, and hencethe locked state is attained in the state having no phase differencebetween clock signals RCLK and FCLK.

However, due to variations of a manufacturing process, an environmenttemperature and power-supply voltage VCC, control voltage VC at the timewhen output clock signal CLK of VCO 130 attains to X (Hz) is easilyvaried from Y (V). Moreover, when the PLL circuit is operated at afrequency other than X (Hz), control voltage VC in the locked state is avalue different from Y (V). Therefore, in such cases, charging currentIc and discharging current Id are unequal, and an offset occurs.

Disclosure of the Invention

Therefore, a main object of the present invention is to provide a clocksynchronizer capable of inhibiting occurrence of an offset.

An object of the present invention can be achieved by providing a clocksynchronizer generating a second clock signal synchronized with a firstclock signal, including a phase difference detection circuit detecting aphase difference between the first and second dock signals, and settinga first control signal to be at an activated level for a time periodcorresponding to the phase difference; a loop filter connected to apredetermined node; a current-supply circuit supplying current to theloop filter in response to the first control signal from the phasedifference detection circuit; and a clock generating circuit generatingthe second dock signal in accordance with a potential of thepredetermined node. The current-supply circuit includes a variablecurrent source whose output current can be controlled, a first switchingcircuit passing output current of the variable current source throughthe loop filter in response to that the first signal is set to be at theactivated level, and a first control circuit: controlling the variablecurrent source such that predetermined constant current flows from thevariable current source to the loop filter, based on the potential ofthe predetermined node.

A main advantage of the present invention is that the variable currentsource is controlled such that constant current flows from the variablecurrent source to the loop filter, based on the potential of thepredetermined node, so that constant current can flow from the variablecurrent source to the loop filter even when the potential of thepredetermined node is varied, and thus occurrence of an offset can beinhibited.

Preferably, the variable current source includes a first transistor of afirst conductivity type whose input electrode receives a first controlpotential. The first switching circuit connects the first transistorbetween a line of a first power-supply potential and the loop filter inresponse to that the first control signal is set to be at the activatedlevel, and the first control circuit controls the first controlpotential such that predetermined constant current flows through thefirst transistor connected between the line of the first power-supplypotential and the loop filter, based on the potential of thepredetermined node. In this case, the potential of the input electrodeof the first transistor is controlled such that constant current flowsthrough the first transistor, based on the potential of thepredetermined node, so that constant current can flow through the firsttransistor even when the potential of the predetermined node is varied,and thus occurrence of the offset can be inhibited.

More preferably, the first control circuit includes a second transistorof a first conductivity type whose first electrode is connected to theline of the first power-supply potential, and whose input electrode isconnected to a second electrode of the second transistor, and outputtingthe first control potential from the second electrode; a thirdtransistor of a second conductivity type whose first electrode isconnected to a second electrode of the second transistor and whose inputelectrode receives the potential of the predetermined node; and a firstresistance element connected between a second electrode of the thirdtransistor and a line of a second power-supply potential. Thisfacilitates constitution of the first control circuit.

More preferably, the first control circuit further includes a secondresistance element connected between the second electrode of the secondtransistor and the line of the second power-supply potential. In thiscase, even when the potential of the predetermined node is set as thesecond power-supply potential and the third transistor is renderednon-conductive, current can flow through the first and secondtransistors, and thus the current-supply circuit can be prevented frombeing inoperative.

More preferably, the variable current source further includes a fourthtransistor of a first conductivity type, connected in parallel with thefirst transistor, whose input electrode receives a constant biaspotential. In this case, even when the potential of the predeterminednode is set as the second power-supply potential and the thirdtransistor is rendered non-conductive, current can flow through thefourth transistor, and thus the current-supply circuit can be preventedfrom being inoperative.

More preferably, the clock synchronizer includes a lock detectioncircuit detecting whether or not the phase difference between the firstand second clock signals is smaller than a predetermined level, settinga lock detection signal to be at an activated level when it is smaller,and setting the lock detection signal to be at an inactivated level whenit is larger. The variable current source further includes a secondtransistor of a first conductivity type whose input electrode receives aconstant bias potential. The first switching circuit connects the firsttransistor between the line of the first power-supply potential and theloop filter when the lock detection signal is at an activated level, andconnecting the second transistor between the line of the firstpower-supply potential and the loop filter when the lock detectionsignal is at an inactivated level, in response to that the first controlsignal is set to be at an activated level. In this case, the secondtransistor through which current flows in accordance with the potentialof the predetermined node is used when not in the locked state, whereasthe first transistor through which constant current flows irrespectiveof the potential of the predetermined node is used when in the lockedstate, so that the lock-in time is made shorter compared to the casewhere only the first transistor is used.

More preferably, the clock synchronizer further includes a lockdetection circuit detecting whether or not the phase difference betweenthe first and second clock signals is smaller than a predeterminedlevel, setting a lock detection signal to be at an activated level whenit is smaller, and setting the lock detection signal to be at aninactivated level when it is larger. The variable current source furtherincludes a second transistor of a first conductivity type whose inputelectrode receives a second control potential. The first switchingcircuit connects the first transistor between the line of the firstpower-supply potential and the loop filter when the lock detectionsignal is at an activated level, and connecting the second transistorbetween the line of the first power-supply potential and the loop filterwhen the lock detection signal is at an inactivated level, in responseto that the first control signal is set to be at an activated level. Thecurrent-supply circuit further includes a second control circuitcontrolling the second control potential such that current flowingthrough the second transistor connected between the line of the firstpower-supply potential and the loop filter is increased in accordancewith a potential difference between the first power-supply potential anda potential of the predetermined node, based on the potential of thepredetermined node. In this case, the second transistor through whichcurrent flows in accordance with the potential difference between thefirst power-supply potential and the potential of the predetermined nodeis used when not in the locked state, whereas the first transistorthrough which constant current flows irrespective of the potential ofthe predetermined node is used when in the locked state, so that thelock-in time is made shorter compared to the case where only the firsttransistor is used.

More preferably, the first control signal is a signal for advancing aphase of the second clock signal. The phase difference detection circuitsets the first control signal to be at an activated level for a timeperiod corresponding to a phase difference between the first and secondclock signals when the phase of the second clock signal is delayed withrespect to the first clock signal, sets a second control signal fordelaying the phase of the second clock signal to be at an activatedlevel for a time period corresponding to a phase difference between thefirst and second dock signals when the phase of the second clock signalis advanced with respect to the first clock signal, and sets the firstand second control signals to be at an activated level for apredetermined period of time when phases of the first and second docksignals agree with each other. The current-supply circuit suppliescurrent of a first polarity to the loop filter in response to that thefirst control signal is set to be at an activated level, and alsosupplies current of a second polarity to the loop filter in response tothat the second control signal is set to be at an activated level. Inthis case, the phase of the second clock signal can be advanced by thefirst control signal, and the phase of the second clock signal can bedelayed by the second control signal.

More preferably, the variable current source further includes a secondtransistor of a second conductivity type whose input electrode receivesa second control potential. The current-supply circuit includes a secondswitching circuit connecting the second transistor between the loopfilter and the line of the second power-supply potential in response tothat the second control signal is set to be at an activated level; and asecond control circuit controlling the second control potential suchthat the predetermined constant current flows through the secondtransistor connected between the loop filter and the line of the secondpower-supply potential, based on a potential of the predetermined node.In this case, even when the potential of the predetermined node isvaried, current of the first polarity and the current of the secondpolarity supplied from the current-supply circuit to the loop filter maybe equalized, and thus occurrence of an offset can be prevented.

Preferably, the clock synchronizer further includes a precharge circuitprecharging the predetermined node to be at a predetermined potential inresponse to application of the first and second power-supply potentials.In this case, the time period from power-up to lock-in can be shortened.

More preferably, the current-supply circuit further includes a secondtransistor of a second conductivity type whose input electrode receivesa constant bias potential, and a second switching circuit connecting thesecond transistor between the loop filter and the line of the secondpower-supply potential in response to that the second control signal isset to be at an activated level. In this case, though current flowingthrough the second transistor varies in accordance with the potential ofthe predetermined node, current flowing through the first transistor ismaintained to be constant, not depending on the potential of thepredetermined node, so that occurrence of an offset can be inhibited.

More preferably, the clock synchronizer further includes a prechargecircuit precharging the predetermined node to be at the firstpower-supply potential in response to application of the first andsecond power-supply potentials. In this case, the time period frompower-up to lock-in can be shortened.

More preferably, the first control signal is a signal for delaying thephase of the second clock signal. The phase difference detection circuitsets the first control signal to be at an activated level for a timeperiod corresponding to a phase difference between the first and secondclock signals when the phase of the second clock signal is advanced withrespect to the first clock signal, sets a second control signal foradvancing the phase of the second clock signal to be at an activatedlevel for a time period corresponding to a phase difference between thefirst and second clock signals when the phase of the second clock signalis delayed with respect to the first clock signal, and sets the firstand second control signals to be at an activated level for apredetermined period of time when the phases of the first and secondclock signals agree with each other. The current-supply circuit suppliescurrent of a first polarity to the loop filter in response to that thefirst control signal is set to be at an activated level, and alsosupplies current of a second polarity to the loop filter in response tothat the second control signal is set to be at an activated level. Inthis case, the phase of the second clock signal can be delayed by thefirst control signal, and the phase of the second clock signal can beadvanced by the second control signal.

More preferably, the current-supply circuit further includes a secondtransistor of a second conductivity type whose input electrode receivesa constant bias potential, and a second switching circuit connecting thesecond transistor between the loop filter and the line of the secondpower-supply potential, in response to that the second control signal isset to be at an activated level. In this case, though current flowingthrough the second transistor varies in accordance with the potential ofthe predetermined node, current flowing through the first transistor ismaintained to the constant, not depending on the potential of thepredetermined node, so that occurrence of the offset can be inhibited.

More preferably, the clock synchronizer further includes a prechargecircuit precharging the predetermined node to be at the firstpower-supply potential in response to application of the first andsecond power-supply potentials. In this case, the time period frompower-up to lock-in can be shortened.

More preferably, the variable current source includes a variablepotential source whose output potential can be controlled, and atransistor whose input electrode receives a constant bias potential. Thefirst switching circuit connects the transistor between an output nodeof the variable potential source and the loop filter, in response tothat the first control signal is set to be at an activated level. Thefirst control circuit controls the variable potential source such thatpredetermined constant current flows through the transistor connectedbetween the output node of the variable potential source and the loopfilter, based on a potential of the predetermined node. In this case,the variable potential source is controlled such that constant currentflows through the transistor, based on the potential of thepredetermined node, so that constant current can flow through thetransistor even when the potential of the predetermined node is varied,and thus occurrence of an offset can be prevented.

More preferably, the variable current source includes a variablepotential source whose output potential can be controlled, and atransistor whose in put electrode receives a constant control potential.The first switching circuit connects the transistor between an outputnode of the variable potential source and the loop filter in response tothat the first control signal is set to be at an activated level. Thefirst control circuit controls the control potential and the variablepotential source such that predetermined constant current flows throughthe transistor connected between the output node of the variablepotential source and the loop filter, based on a potential of thepredetermined node. In this case, the control potential and the variablepotential source are controlled such that constant current flows throughthe transistor, based on the potential of the predetermined node, sothat constant current can flow through the transistor even when thepotential of the predetermined node is varied, and thus occurrence of anoffset can be inhibited.

More preferably, the loop filter includes a resistance element and acapacitor connected in series between the predetermined node and a lineof a reference potential. In this case, charge applied from thecurrent-supply circuit to the loop filter is charged to the capacitor.

An object of the present invention is also achieved by providing a clocksynchronizer generating a second clock signal synchronized with a firstclock signal, including a phase difference detection circuit detecting aphase difference between the first and second clock signals and settinga control signal to be at an activated level for a time periodcorresponding to the phase difference; a loop filter connected to apredetermined node; a current-supply circuit supplying current to theloop filter in response to a control signal from the phase differencedetection circuit; and a clock generating circuit generating the seconddock signal in accordance with a control potential. The current-supplycircuit includes a transistor whose input electrode receives the controlpotential, a switching circuit connecting the transistor between a lineof a power-supply potential and the loop filter, in response to that thecontrol signal is set to be at an activated level, and a control circuitcontrolling the control potential such that predetermined constantcurrent flows through the transistor connected between the line of thepower-supply potential and the loop filter, based on a potential of thepredetermined node.

In this case, the control potential is controlled such that constantcurrent flows through the transistor, based on the potential of thepredetermined node, so that constant current can flow through thetransistor even when the output potential of the predetermined node isvaried, and thus occurrence of an offset can be inhibited. Moreover, thecontrol potential is also used for generating the second clock signal,so that circuit configuration may be simplified.

An object of the present invention is further achieved by providing aclock synchronizer generating a second dock signal synchronized with afirst clock signal, including a phase difference detection circuitdetecting a phase difference between the first and second clock signals,and setting a control signal to be at an activated level for a timeperiod corresponding to the phase difference; a loop filter including aresistance element and a capacitor connected in series between apredetermined node and a line of a reference potential; a current-supplycircuit supplying current to the loop filter in response to a controlsignal from the phase difference detection circuit; and a clockgenerating circuit generating the second clock signal in accordance witha potential of the predetermined node. The current-supply circuitincludes a transistor whose input electrode receives a controlpotential, a switching circuit connecting the transistor between a lineof a power-supply potential and the loop filter, in response to that thecontrol signal is set to be at an activated level, and a control circuitcontrolling the control potential such that predetermined constantcurrent flows through the transistor connected between the line of thepower-supply potential and the loop filter, based on a potential of anode between the resistance element and a capacitor.

In this case, the control potential is controlled such that constantcurrent flows through the transistor, based on the potential of a nodebetween the resistance element and the capacitor of the loop filter, sothat constant current can flow through the transistor even when thepotential of the predetermined node is varied, and thus occurrence of anoffset can be inhibited.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit block diagram showing the configuration of a PLLcircuit according to the first embodiment of the present invention;

FIG. 2 is a time chart illustrating the operation of a phase comparatorshown in FIG. 1;

FIG. 3 is another time chart illustrating the operation of the phasecomparator shown in FIG. 1;

FIG. 4 is a further time chart illustrating the operation of the phasecomparator shown in FIG. 1;

FIG. 5 is a circuit block diagram showing in detail the configuration ofa control circuit shown in FIG. 1;

FIG. 6 is a circuit diagram showing the configuration of VCO shown inFIG. 1;

FIG. 7 is a circuit block diagram showing a modification of the firstembodiment;

FIG. 8 is a circuit block diagram showing another modification of thefirst embodiment;

FIG. 9 is a circuit block diagram showing a further modification of thefirst embodiment;

FIG. 10 is a circuit diagram showing a yet another modification of thefirst embodiment;

FIG. 11 is a circuit diagram showing the configuration of a charge pumpcircuit included in a PLL circuit according to the second embodiment ofthe present invention;

FIG. 12 is a circuit diagram showing the configuration of a biasgenerating circuit for generating a bias potential shown in FIG. 11;

FIG. 13 is a circuit diagram showing the configuration of a controlcircuit included in a PLL circuit according to the third embodiment ofthe present invention;

FIG. 14 is a circuit diagram showing the configuration of a prechargecircuit included in a PLL circuit according to the fourth embodiment ofthe present invention;

FIG. 15 is a circuit block diagram showing the configuration of a PLLcircuit according to the fifth embodiment of the present invention;

FIG. 16 is a circuit block diagram showing the configuration of a PLLcircuit according to the sixth embodiment of the present invention;

FIG. 17 is a circuit block diagram showing the configuration of a PLLcircuit according to the seventh embodiment of the present invention;

FIG. 18 is a circuit block diagram showing the configuration of a PLLcircuit according to the eighth embodiment of the present invention;

FIG. 19 is a circuit diagram showing the configuration of a controlcircuit 86 shown in FIG. 18;

FIG. 20 is a circuit diagram showing the configuration of a controlcircuit 87 shown in FIG. 18;

FIG. 21 is a circuit block diagram showing the configuration of a PLLcircuit according to the ninth embodiment of the present invention;

FIG. 22 is a circuit block diagram showing the configuration of a PLLcircuit according to the tenth embodiment of the present invention; and

FIG. 23 is a circuit block diagram showing the configuration of theconventional PLL circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

A clock synchronizer according to the present invention will bedescribed below with reference to the drawings.

First Embodiment

FIG. 1 is a circuit block diagram showing the configuration of a PLLcircuit according to the first embodiment of the present invention. InFIG. 1, the PLL circuit includes a phase comparator 1, a charge pumpcircuit 2, control circuits 7, 8, a loop filter 9, a VCO 12, and afrequency divider 13.

Phase comparator 1 compares the phase of a reference clock signal RCLK,which is an external clock signal, and the phase of a feedback clocksignal FCLK, and outputs signals UP, DOWN based on the comparisonresult. When the phase of feedback clock signal FCLK is advanced withrespect to the phase of reference clock signal RCLK, as shown in FIG. 2,signal UP is lowered to “L” level in a pulsive manner for a certainperiod of time in response to the rising edge of reference clock signalRCLK, and signal DOWN is raised to “H” level in response to the risingedge of feedback clock signal FCLK and is lowered to “L” level inresponse to the rising edge of signal UP. Thus, in this case, the pulsewidth of signal DOWN is wider than the pulse width of signal UP.

When the phase of feedback clock signal FCLK is delayed with respect tothe phase of reference clock signal RCLK, as shown in FIG. 3, signalDOWN is raised to “H” level in a pulsive manner for a certain period oftime in response to the rising edge of feedback clock signal FCLK, andsignal UP is lowered to “L” level in response to the rising edge ofreference clock signal RCLK and is raised to “H” level in response tothe trailing edge of signal DOWN. Therefore, in this case, the pulsewidth of signal UP is wider than the pulse width of signal DOWN.

When the phase of feedback clock signal FCLK and the phase of referenceclock signal RCLK agree with each other, as shown in FIG. 4, signal UPis lowered to “L” level in a pulsive manner for a certain period of timein response to the rising edges of clock signals RCLK, FCLK, and signalDOWN is raised to “H” level in a pulsive manner for a certain period oftime in response to the rising edges of clock signals FCLK, RCLK.Therefore, in this case, the pulse width of signal UP is equal to thepulse width of signal DOWN.

Referring back to FIG. 1, charge pump circuit 2 includes a P-channel MOStransistor 3 and a switching element 4 connected in series between theline of a power-supply potential VCC and a node N2; and a switchingelement 5 and an N-channel MOS transistor 6 connected in series betweennode N2 and the line of a ground potential GND. The gate of P-channelMOS transistor 3 receives a control potential VCP generated at controlcircuit 7. P-channel MOS transistor 3 constitutes a variable currentsource 2 a, through which current Ic of a value according to controlpotential VCP flows. The gate of N-channel MOS transistor 6 receives acontrol potential VCN generated at control circuit 8. N-channel MOStransistor 6 constitutes a variable current source 2 b, through whichcurrent Id of a value according to control potential VCN flows.

Switching element 4 conducts for a period during which signal UP is atthe activated level of “L” level. Switching element 4 is constituted bya transistor, for example, a P-channel MOS transistor connected betweenthe drain of P-channel MOS transistor 3 and node N2, the gate of whichreceiving signal UP.

Switching element 5 conducts for a period during which signal DOWN is atthe activated level of “H” level. Switching element 5 is constituted bya transistor, for example, an N-channel MOS transistor connected betweenthe drain of N-channel MOS transistor 6 and node N2, the gate of whichreceiving signal DOWN.

Control circuit 7 includes, as shown in FIG. 5, a P-channel MOStransistor 21, an N-channel MOS transistor 22 and a resistance element23 connected in series between the line of power-supply potential VCCand the line of ground potential GND. The gate of P-channel MOStransistor 21 is connected to the drain thereof and also to the gate ofP-channel MOS transistor 3 in charge pump circuit 2. A gate potential ofP-channel MOS transistor 21 is to be control potential VCP. The gate ofN-channel MOS transistor 22 is connected to node N2.

This PLL circuit is designed to be in a locked state when the potentialof node N2, i.e. control potential VC, is VCC/2. If control potential VCbecomes higher than VCC/2, the resistance value of N-channel MOStransistor 22 is reduced, lowering control potential VCP. Thus, thereduced amount of current Ic that is generated due to increase of drainpotential VC of P-channel MOS transistor 3 and the increased amount ofcurrent Ic that is generated due to lowering of gate potential VCP ofP-channel MOS transistor 3 are canceled out, causing no variation in thecurrent flowing through P-channel MOS transistor 3.

On the contrary, if control potential VC becomes lower than VCC/2, theresistance value of N-channel MOS transistor 22 is increased, makingcontrol potential VCP higher. Thus, the increased amount of current Icthat is generated due to reduction of drain potential VC of P-channelMOS transistor 3 and the reduced amount of current Ic that is generateddue to increase of gate potential VCP of P-channel MOS transistor 3 arecanceled out, causing no variation in the current flowing throughP-channel MOS transistor 3. Therefore, current Ic flowing throughP-channel MOS transistor 3 when switching element 4 is conducting ismaintained to be constant, irrespective of the level of controlpotential VC.

Control circuit 8 includes, as shown in FIG. 5, a resistance element 24,a P-channel MOS transistor 25 and an N-channel MOS transistor 26connected in series between the line of power-supply potential VCC andthe line of ground potential GND. The gate of N-channel MOS transistor26 is connected to the drain thereof, and also to the gate of N-channelMOS transistor 6 in charge pump circuit 2. The gate potential ofN-channel MOS transistor 26 is to be control potential VCN. The gate ofP-channel MOS transistor 25 is connected to node N2.

If control potential VC becomes higher than VCC/2, the resistance valueof P-channel MOS transistor 25 is increased, lowering control potentialVCN. Therefore, the increased amount of current Id that is generated dueto increase of drain potential VC of N-channel MOS transistor 6 and thereduced amount of current Id that is generated due to lowering of gatepotential VCP of N-channel MOS transistor 6 are canceled out, causing novariation in current Id flowing through N-channel MOS transistor 6.

On the contrary, if control potential VC becomes lower than VCC/2, theresistance value of P-channel MOS transistor 25 is reduced, and controlpotential VCN is increased. Therefore, the reduced amount of current Idthat is generated due to lowering of drain potential VC of N-channel MOStransistor 6 and the increased amount of current Id that is generateddue to increase of gate potential VCP of N-channel MOS transistor 6 arecanceled out, causing no variation in current Id flowing throughN-channel MOS transistor 6. Therefore, there is no change in current Idflowing through N-channel MOS transistor 6 when switching element 5 isconducting, irrespective of the level of control potential VC. From thedescription above, charging current Ic and discharging current Id arealways maintained at the same value, and unlike the conventional case,no offset occurs.

Loop filter 9 includes a resistance element 10 and a capacitor 11connected in series between node N2 and the line of ground potentialGND. Capacitor 11 is charged and discharged by charge pump circuit 2.

VCO 12 includes, as shown in FIG. 6, inverters 31.1 to 31.n (wherein nis an odd number equal to or higher than 3), 32; P-channel MOStransistors 33, 34, 35.1 to 35.n; N-channel MOS transistors 36, 37, 38.1to 38.n; and a resistance element 39.

P-channel MOS transistor 33, N-channel MOS transistor 36 and resistanceelement 39 is connected in series between the line of power-supplypotential VCC and the line of ground potential GND. P-channel MOStransistor 34 and N-channel MOS transistor 37 are connected in seriesbetween the line of power-supply potential VCC and the line of groundpotential GND. The gate of N-channel MOS transistor 36 receives controlpotential VC. The gates of P-channel MOS transistors 33, 34 are bothconnected to the drain of P-channel MOS transistor 33. P-channel MOStransistors 33 and 34 constitute a current mirror circuit. The gate ofN-channel MOS transistor 37 is connected to the drain thereof.

Current of a value according to control potential VC flows throughN-channel MOS transistor 36. MOS transistors 36 and 33 are connected inseries, MOS transistors 33 and 34 constitute the current mirror circuit,and MOS transistors 34 and 37 are connected in series, so that currentaccording to control potential VC flows through MOS transistors 34, 37.

Inverters 31.1 to 31.n are ring-connected. N-channel MOS transistors35.1 to 35.n are respectively connected between the line of power-supplypotential VCC and the power-supply nodes of inverters 31.1 to 31.n, andthe gate of each transistor is connected altogether to the gate ofP-channel MOS transistor 34. P-channel MOS transistors 38.1 to 38.n arerespectively connected between the line of ground potential GND andground nodes of inverters 31.1 to 31.n, and the gate of each transistoris altogether connected to the gate of N-channel MOS transistor 37.Current of a value according to control potential VC flows through MOStransistors 35.1 to 35.n and 38.1 to 38.n. An output signal of inverter31.n is inverted at inverter 32 to be an internal clock signal CLK.

When control potential VC is increased, the resistance value ofN-channel MOS transistor 36 is reduced, increasing the current flowingthrough P-channel MOS transistors 33, 34, 35.1 to 35.n and N-channel MOStransistors 36, 37, 38.1 to 38.n, and drivability of inverters 31.1 to31.n is increased and the frequency of internal clock signal CLK becomeshigher.

When control potential VC is lowered, the resistance value of N-channelMOS transistor 36 is increased, reducing the current flowing throughP-channel MOS transistors 33, 34, 35.1 to 35.n and N-channel MOStransistors 36, 37, 38.1 to 38.n, and drivability of inverters 31.1 to31.n is also reduced and the frequency of internal clock signal CLK islowered.

Referring back to FIG. 1, internal clock signal CLK generated at VCO 12is applied to an internal circuit of the semiconductor integratedcircuit device and also to a frequency divider 13. Frequency divider 13divides the frequency of internal clock signal CLK by N to generateclock signal FCLK. Clock signal FCLK is returned to phase comparator 1.

Next, the operation of the PLL circuit shown in FIGS. 1 to 6 will bedescribed. When the phase of feedback clock signal FCLK is advanced withrespect to the phase of reference clock signal RCLK, the pulse width ofsignal DOWN is wider than the pulse width of signal UP, and the amountof charge flowing into node N2 becomes smaller than the amount of chargeflowing out of node N2, gradually lowering control potential VC. Thisgradually lowers the frequency of output clock signal CLK of VCO 12,resulting in agreement of the phase of feedback clock signal FCLK withthe phase of reference clock signal RCLK.

When the phase of feedback clock signal FCLK is delayed with respect tothe phase of reference clock signal RCLK, the pulse width of signal UPis wider than the pulse width of signal DOWN, and the amount of chargeflowing into node N2 becomes larger than the amount of charge flowingout of node N2, gradually raising control potential VC. This graduallyraises the frequency of output clock signal CLK of VCO 12, resulting inagreement of the phase of feedback clock signal FCLK with the phase ofreference clock signal RCLK.

When the phase of feedback clock signal FCLK agrees with the phase ofreference clock signal RCLK and when in a locked state, the pulse widthof signals UP and DOWN are equal to each other, the amount of chargeflowing into node N2 and the amount of charge flowing out of node N2 areequal to each other, and there is no change in control potential VC.Therefore, the frequency of output clock signal CLK of VCO 12 ismaintained to be constant.

In the first embodiment, when control potential VC is higher than VCC/2,gate potentials VCP, VCN of MOS transistors 3, 6 are lowered, and whencontrol potential VC is lower than VCC/2, the gate potential VCP, VCN ofMOS transistors 3, 6 are increased, so that current Ic, Id flowingthrough MOS transistors 3, 6 at the time of conduction of switchingelements 4, 6 can be maintained to be constant, irrespective of thelevel of control potential Vc. Therefore, even though there arevariations in the manufacturing process, the environment temperature,power-supply voltage VCC and so forth, or when a frequency of a valueother than the design value is used for operation, no offset occurs.

Various modifications of the first embodiment will be described below.The modification in FIG. 7 is different from the PLL circuit in FIG. 1in that P-channel MOS transistor 3 and switching element 4 are exchangedin their positions, and also N-channel MOS transistor 6 and switchingelement 5 are exchanged in their positions. Also in this modification,the same effect as that of the PLL circuit in FIG. 1 can be obtained.

In the modification shown in FIG. 8, control circuits 7, 8 generatecontrol potentials VCP, VCN in accordance with a potential VC of a nodeN11 between resistance element 10 and capacitor 11 of loop filter 9.Potential VC of node N11 is more stable than potential VC of node N2, sothat more stable control of MOS transistors 3, 6 can be achieved.

Control circuit 7 shown in FIG. 5 has the same configuration as that ofthe portion constituted by P-channel MOS transistor 33, N-channel MOStransistor 36 and resistance element 39 of VCO 12 shown in FIG. 6.Therefore, in the modification shown in FIG. 9, MOS transistors 33, 36and resistance element 39 in VCO 12 are omitted, and control potentialVCP generated at control circuit 7 is applied to the gates of P-channelMOS transistors 34, 35.1 to 35.n in VCO 12. In this modification, inaddition to attainment of the same effect as that of the PLL circuit inFIG. 1, the layout area can be reduced by the area that would beoccupied by MOS transistors 33, 36 and resistant element 29.

Moreover, though in FIGS. 1 to 9, the case where the present inventionis applied to the PLL circuit was described, the present invention isapplicable to other clock synchronizers such as DLL (Delay Locked Loop)circuit. FIG. 10 is a circuit block diagram showing the configuration ofa DLL circuit to which the present invention is applied. In FIG. 10, theDLL circuit is different from the PLL circuit in FIG. 1 in that VCO 12and frequency divider 13 are replaced by a voltage control delay circuit40. Voltage control delay circuit 40 delays reference clock signal RCLKby a time period corresponding to control voltage VC, to generate aninternal clock signal CLK. Internal clock signal CLK is returned tophase comparator 1. Generation of an offset is prevented also in thismodification.

Second Embodiment

In FIG. 5, if, for some reason, node N2 has power-supply potential VCC,current Ic flowing through P-channel MOS transistor 3 at the time ofconduction of switching element 4 will be at the maximal value, while nocurrent Id flows through N-channel MOS transistor 6 even thoughswitching element 5 is rendered conductive. Furthermore, if node 2 hasground potential GND for some reason, current Id flowing throughN-channel MOS transistor 6 at the time of conduction of switchingelement 5 will be at the maximal value, while no current Ic flowsthrough P-channel MOS transistor 3 even though switching element 4 isrendered conductive. Therefore, when node N2 has power-potential VCC orground potential GND, the PLL circuit of the first embodiment will beinoperative. This problem is solved in the second embodiment.

FIG. 11 is a circuit diagram showing a substantial part of a PLL circuitaccording to the second embodiment of the present invention. In FIG. 11,this PLL circuit is different from the PLL circuit in FIG. 1 in thatcharge pump circuit 2 is replaced by a charge pump circuit 41.

Charge pump circuit 41 includes MOS transistors 42, 43 connectedrespectively in parallel with P-channel MOS transistors 3, 6 of chargepump circuit 2. The gate of P-channel MOS transistor 42 receives aconstant bias potential VBP, and the gate of N-channel MOS transistor 43receives a constant bias potential VBN. P-channel MOS transistors 3, 42constitute a variable current source 41a, and N-channel MOS transistors6, 43 constitute a variable current source 41b. FIG. 12 is a circuitdiagram showing the configuration of a bias potential generating circuit44 generating bias potentials VBP, VBN. In FIG. 12, bias potentialgenerating circuit 44 includes P-channel MOS transistors 45, 46,N-channel MOS transistor 47, and a resistance element 48.

MOS transistors 45 and 47, and P-channel MOS transistor 46 andresistance element 48 are respectively connected in series between thelines of power-supply potentials VCC and the lines of ground potentialsGND. The gates of P-channel MOS transistors 45, 46 are both connected tothe drain of P-channel MOS transistor 46. P-channel MOS transistors 45,46 constitute a current mirror circuit. The gate potentials of P-channelMOS transistors 45, 46 are to be bias potential VBP. The gate ofN-channel MOS transistor 47 is connected to the drain thereof. The gatepotential of N-channel MOS transistor 47 is to be bias potential VBN.

Constant current determined by the resistance value of resistanceelement 48 and power-supply voltage VCC flows through P-channel MOStransistor 46 and resistance element 48. P-channel MOS transistors 45,46 constitute a current mirror circuit and MOS transistors 45, 47 areserially connected, so that constant current of a value according to thecurrent flowing through P-channel MOS transistor 46 and resistanceelement 48 flows through MOS transistors 45, 47. Furthermore, the gateof P-channel MOS transistor 42 of charge pump circuit 41 is connected tothe gates of P-channel MOS transistors 45, 46, and the gate of N-channelMOS transistor 43 of charge pump circuit 41 is connected to the gate ofN-channel MOS transistor 47, so that constant current of a valueaccording to the current flowing through P-channel MOS transistor 46 andresistance element 48 flows through MOS transistors 42, 43.

Therefore, in the second embodiment, even when node N2 has power-supplypotential VCC and thus no current flows through N-channel MOS transistor6, current flows through N-channel MOS transistor 43, so that the PLLcircuit operates. Moreover, even when node N2 has ground potential GNDand thus no current flows through P-channel MOS transistor 3, currentflows through P-channel MOS transistor 42, so that the PLL circuit stilloperates. The other configurations and operations are the same as thoseof the PLL circuit in FIG. 1, so that the description thereof will notbe repeated.

Third Embodiment

FIG. 13 is a circuit diagram showing a substantial part of a PLL circuitaccording to the third embodiment of the present invention. In FIG. 13,this PLL circuit is different from the PLL circuit in FIG. 1 in thatcontrol circuits 7, 8 are replaced by control circuits 50, 51,respectively.

Control circuit 50 includes a resistance element 52 connected inparallel with N-channel MOS transistor 22 and resistance element 23 ofcontrol circuit 7 shown in FIG. 5. Control circuit 51 includes aresistance element 53 connected in parallel with resistance element 24and P-channel MOS transistor 25 of control circuit 8 shown in FIG. 5.

Therefore, in the third embodiment, even when node N2 has power-supplypotential VCC and thus no current flows through P-channel MOS transistor25, current flows through resistance element 53 and N-channel MOStransistor 26 and current flows through N-channel MOS transistor 6 ofthe charge pump circuit, so that the PLL circuit operates. Moreover,even when node N2 has power-supply potential VCC and thus no currentflows through N-channel MOS transistor 22, current flows throughP-channel MOS transistor 21 and resistance element 52 and current flowsthrough P-channel MOS transistor 3 of charge pump circuit 2, so that thePLL circuit operates. . The other configurations and operations are thesame as those of the PLL circuit in FIG. 1, so that the descriptionthereof will not be repeated.

Fourth Embodiment

In the conventional PLL circuit shown in FIG. 23, assuming thatpotential VC of node N122 is ground potential GND before thepower-supply is turned on, and potential VC of node N122 in the lockedstate is VCC/2, current Ic flowing through P-channel MOS transistor 123supplies charge to node N122 for a period from the power-up until thelocked state is reached. Current Ic at this moment is increased aspotential VC of node N122 is lowered. Thus, in the conventional PLLcircuit, while there is a disadvantage in that current Ic and Iddisagree with each other generating an offset, there is an advantage inthat the time period from the power-up to the locked state is short.

Whereas, in the PLL circuit of FIG. 1, current Ic, Id are controlled tobe constant irrespective of potential VC of node N2. Therefore, in thePLL circuit of FIG. 1, while there is an advantage in that no offsetoccurs even though potential VC of node N2 is varied, there is adisadvantage in that the time period from the power power-up to thelocked state is longer than that of the conventional case. This problemis solved in the fourth embodiment.

FIG. 14 is a circuit diagram showing a substantial part of a PLL circuitaccording to the fourth embodiment of the present invention. In FIG. 14,this PLL circuit is different from the PLL circuit of FIG. 1 in that aprecharge circuit 60 is added.

Precharge circuit 60 includes a P-channel MOS transistor 63, aresistance elements 64, 65 and an N-channel MOS transistor 66 connectedin series between the line of power-supply potential VCC and the line ofground potential GND, and an inverter 67. A power-on reset signal/POR isinput directly into the gate of P-channel MOS transistor 63, and also isinput into the gate of N-channel MOS transistor 66 via inverter 67.Signal /POR is a signal set to be at an activated level of “L” level,for a predetermined period of time from the power-up. A node betweenresistance elements 64 and 65 is connected to node N2. Resistanceelements 64 and 65 have the same resistance value.

Before the power is turned on, node N2 is assumed to have groundpotential GND. When the power is turned on and signal /POR is lowered tothe activated level of “L” level, MOS transistors 63, 66 are renderedconductive, and potential VC of node N2 attains to potential VCC/2obtained by dividing power-supply voltage VCC by resistance elements 64and 65.

Therefore, in the fourth embodiment, potential VC of node N2 can beraised rapidly at power-up, and therefore the time period from thepower-up to the locked state is shortened.

It is noted that, though resistance elements 64 and 65 have the sameresistance value in the fourth embodiment, the ratio of the resistancevalues of resistance elements 64 and 65 may be changed to prechargepotential VC of node N2 to be at a desired potential.

Fifth Embodiment

FIG. 15 is a circuit block diagram showing the configuration of a PLLcircuit according to the fifth embodiment of the present invention.Referring to FIG. 15, this PLL circuit is different from the PLL circuitin FIG. 1 in that control circuit 8 is removed and a constant biaspotential VBN is applied to the gate of N-channel MOS transistor 6, andin that a precharge circuit 70 is added. Precharge circuit 70 includes aP-channel MOS transistor 71. P-channel MOS transistor 71 is connectedbetween the line of power-supply potential VCC and node N2, and the gatethereof receives a power-on reset signal/POR.

Before the power is turned on, node N2 is assumed to have groundpotential GND. When the power is turned on and signal/POR is lowered toan activated level of “L” level for a certain period of time, P-channelMOS transistor 71 conducts in a pulsive manner and node N2 is prechargedto be at power-supply potential VCC. N-channel MOS transistor 6 incharge pump circuit 2 passes larger current therethrough as potential VCof node N2 becomes higher. Therefore, compared to the PLL circuit inFIG. 1 where current Ic flowing through N-channel MOS transistor 6 wasmade constant irrespective of the level of potential VC of node N2, thetime period from the power-up until the potential of node N2 reaches thepotential at lock-in can be shorter.

Moreover, current flowing through P-channel MOS transistor 3 is madeconstant by control circuit 7, so that occurrence of an offset can beinhibited compared to the conventional case where current Ic flowingthrough P-channel MOS transistor 3 was reduced/increased as current Idflowing through N-channel MOS transistor 6 was increased/decreased.

Sixth Embodiment

FIG. 16 is a circuit block diagram showing the configuration of a PLLcircuit according to the sixth embodiment of the present invention.Referring to FIG. 16, this PLL circuit is different from the PLL circuitof FIG. 1 in that control circuit 7 is removed and a constant biaspotential VBP is applied to the gate of P-channel MOS transistor 3, andthat a predischarge circuit 72 is added. Predischarge circuit 72includes an N-channel MOS transistor 73. N-channel MOS transistor 73 isconnected between node N2 and the line of ground potential GND, and thegate thereof receives a complementary signal POR of the power-on resetsignal.

It is assumed that node N2 has an arbitrary potential before the poweris turned on. When the power is turned on and signal POR is raised to anactivated level of “H” level for a certain period of time, N-channel MOStransistor 73 conducts in a pulsive manner and node N2 is predischargedto be at ground potential GND. P-channel MOS transistor 3 in charge pumpcircuit 2 passes larger current therethrough as potential VC of node N2is lowered. Therefore, compared to the PLL circuit of FIG. 1 wherecurrent Id flowing through P-channel MOS transistor 3 was made constantirrespective of the level of potential VC of node N2, the time periodfrom the power-up until the potential of node N2 reaches the potentialat lock-in can be shorter.

Furthermore, current flowing through N-channel MOS transistor 6 is madeconstant by control circuit 8, so that occurrence of an offset can beinhibited compared to the conventional case where current Id flowingthrough N-channel MOS transistor 6 was reduced/increased as current Icflowing through P-channel MOS transistor 3 was increased/reduced.

Seventh Embodiment

FIG. 17 is a circuit block diagram showing the configuration of an PLLcircuit according to the seventh embodiment of the present invention.Referring to FIG. 17, this PLL circuit is different from the PLL circuitof FIG. 1 in that charge pump circuit 2 is replaced by a charge pumpcircuit 80, and that a lock detector 85 is added.

Lock detector 85 sets a lock detection signal φL at an activated levelof “H” level when the phase difference between reference clock signalRCLK and feedback clock signal FCLK is smaller than a predeterminedlevel, whereas it sets lock detection signal φL at an inactivated levelof “L” level when the phase difference between reference clock signalRCLK and feedback clock signal FCLK is larger than the predeterminedlevel.

Charge pump circuit 80 is different from charge pump circuit 2 in that aP-channel MOS transistor 81, an N-channel MOS transistor 84, andselectors 82, 83 are added.

The source of P-channel MOS transistor 81 receives power-supplypotential VCC, and the gate thereof receives a constant bias potentialVBP. P-channel MOS transistors 3, 81 constitute a variable currentsource 80 a. Selector 82 is interposed between the drains of P-channelMOS transistors 3, 81 and one electrode of switching element 4, toconnect the drain of P-channel MOS transistor 81 to the one electrode ofswitching element 4 when signal φL is at the inactivated level of “L”level, and to connect the drain of P-channel MOS transistor 3 to the oneelectrode of switching element 4 when signal φL is at the activatedlevel of “H” level.

The source of N-channel MOS transistor 84 receives ground potential GND,and the gate thereof receives a constant bias potential VBN. N-channelMOS transistors 6, 84 constitute a variable current source 80 b.Selector 83 is interposed between the drains of N-channel MOStransistors 6, 84 and one electrode of switching element 5, to connectthe drain of N-channel MOS transistor 84 to the one electrode ofswitching element 5 when signal φL is at the inactivated level of “L”level, and to connect the drain of N-channel MOS transistor 6 to the oneelectrode of switching element 5 when signal φL is at the activatedlevel of “H” level.

Next, the operation of this PLL circuit will be described. When the PLLcircuit has not reached the locked state such as at power-up, signal φLis lowered to the inactivated level of “L” level, and the drain ofP-channel MOS transistor 81 is connected to the one electrode ofswitching element 4 by selector 82, while the drain of N-channel MOStransistor 84 is connected to the one electrode of switching element 5by selector 83. In this case, the PLL circuit in FIG. 17 has the sameconfiguration as that of the conventional PLL circuit. Therefore, as inthe conventional case, this PLL circuit rapidly reaches the lockedstate. However, an offset occurs in this state.

When the PLL circuit reaches the locked state, signal φL is raised tothe activated level of “H” level, and the drain of P-channel MOStransistor 3 is connected to the one electrode of switching element 4 byselector 82, while the drain of N-channel MOS transistor 6 is connectedto the one electrode of switching element 5 by selector 83. In thiscase, the PLL circuit in FIG. 17 has the same configuration as that ofthe PLL circuit in FIG. 1. Therefore, no offset occurs even thoughcontrol potential VC at lock-in is varied.

Eighth Embodiment

FIG. 18 is a circuit block diagram showing the configuration of a PLLcircuit according to the eighth embodiment of the present invention. InFIG. 18, this PLL circuit is different from the PLL circuit in FIG. 17in that control circuits 86, 87 are added and control potentials VCP′,VCN′ generated at control circuits 86, 87 are input into the gates ofMOS transistors 81, 84 in place of bias potentials VBP, VBN.

Control circuit 86 includes, as shown in FIG. 19, a resistance element91, P-channel MOS transistors 92, 93, and N-channel MOS transistors 94,95. MOS transistors 92 and 94, and resistance element 91 and MOStransistors 93, 95 are respectively connected in series between thelines of power-supply potential VCC and the lines of ground potentialGND. The gate of P-channel MOS transistor 93 receives a controlpotential VC. The gates of N-channel MOS transistors, 94, 95 are bothconnected to the drain of N-channel MOS transistor 95. N-channel MOStransistors 94 and 95 constitute a current mirror circuit. The gate ofP-channel MOS transistor 92 is connected to the drain thereof. The gatepotential of P-channel MOS transistor 92 is to be control potentialVCP′.

MOS transistors 94, 95 constitute the current mirror circuit, MOStransistors 92 and 94 are connected in series, and the gate of P-channelMOS transistor 29 is connected to the gate of P-channel MOS transistor81 in charge pump circuit 80, so that current corresponding to thecurrent flowing through P-channel MOS transistor 97 flows throughP-channel MOS transistor 81.

When control potential VC is made higher, the resistance value ofP-channel MOS transistor 93 is increased, reducing current flowingthrough resistance element 91 and MOS transistors 93, 95, and currentflowing through P-channel MOS transistor 81 is also reduced. Whencontrol potential VC is lowered, the resistance value of P-channel MOStransistor 93 is reduced, increasing current flowing through resistanceelement 91 and MOS transistors 93, 95, and current flowing throughP-channel MOS transistor 81 is also increased.

In control circuit 87, as shown in FIG. 20, MOS transistors 101, 103,and MOS transistors 102, 104 and resistance element 105 are respectivelyconnected in series between the lines of power-supply potential VCC andthe lines of ground potential GND. The gate of N-channel MOS transistor104 receives control potential VC. The gates of P-channel MOStransistors 101, 102 are both connected to the drain of P-channel MOStransistor 102. P-channel MOS transistors 101 and 102 constitute acurrent mirror circuit. The gate of N-channel MOS transistor 103 isconnected to the drain thereof The gate potential of N-channel MOStransistor 103 is to be control potential VCN′.

N-channel MOS transistors 101 and 102 constitute a current mirrorcircuit, MOS transistors 101, 103 are connected in series, and the gateof N-channel MOS transistor 103 is connected to the gate of N-channelMOS transistor 84 of charge pump circuit 80, so that current of a valuecorresponding to the current flowing through N-channel MOS transistor104 flows through N-channel MOS transistor 84.

As control potential VC is increased, the resistance value of N-channelMOS transistor 104 is lowered, increasing the current flowing throughMOS transistors 102, 104 and resistance element 105, and the currentflowing through N-channel MOS transistor 84 is also increased. Ascontrol potential VC is lowered, the resistance value of N-channel MOStransistor 104 is lowered, reducing the current flowing through MOStransistors 102, 104 and resistance element 105, and current flowingthrough N-channel MOS transistor 84 is also reduced.

Next, the operation of the PLL circuit will be described. When the PLLcircuit is not in the locked state, signal φL is set to be at theinactivated level of “L” level, and the drain of P-channel MOStransistor 81 is connected to one electrode of switching element 4 byselector 82, while the drain of N-channel MOS transistor 84 is connectedto one electrode of switching element 5 by selector 83.

When control potential VC is lower than VCC/2, control potential VCP′ islowered and the current flowing through P-channel MOS transistor 81 isincreased, while control potential VCN′ is lowered and the currentflowing through N-channel MOS transistor 84 is reduced.

When control potential VC is higher than VCC/2, control potential VCP′is increased and the current flowing through P-channel MOS transistor 81is reduced, while control potential VCN′ is increased and the currentflowing through N-channel MOS transistor 84 is increased.

Therefore, the locked state can be reached in a shorter time periodcompared to the case with the PLL circuit in FIG. 17 in which theconstant bias potential was applied to the gates of MOS transistors 81,84. The other configurations and operations are the same as those of thePLL circuit in FIG. 17, so that the description thereof will not berepeated.

Ninth Embodiment

FIG. 21 is a circuit block diagram showing the configuration of a PLLcircuit according to the ninth embodiment of the present invention. InFIG. 21, this PLL circuit is different from the PLL circuit in FIG. 1 inthat charge pump circuit 2 is replaced by a charge pump circuit 110.Charge pump circuit 110 is different from charge pump circuit 2 in that,in place of control potentials VCP, VCN, constant bias potentials VBP,VBN are applied, respectively, to the gates of MOS transistors 3, 6, andthat, in place of power-supply potential VCC and ground potential GND,output potentials V1, V2 of variable voltage sources 111, 112 areapplied, respectively, to the sources of MOS transistors 3, 6.

Variable voltage sources 111, 112 are controlled by control circuits 7,8, respectively. Variable voltage source 111 and P-channel MOStransistor 3 constitute a variable current source 110 a, and variablevoltage source 112 and N-channel MOS transistor 6 constitute a variablecurrent source 110 b.

As control potential VC is increased, output potentials V1, V2 ofvariable voltage sources 110, 111 are also increased, and as controlpotential VC is lowered, output potentials V1, V2 of variable voltagesources 110, 111 are also lowered, and thus V1-VC and VC-V2 are alwaysmaintained to be constant. Therefore, even though control potential VCis varied, current Ic flowing through P-channel MOS transistor 3 at thetime of conduction of switching element 4 and current Id flowing throughN-channel MOS transistor 6 at the time of conduction of switchingelement 5 are always maintained to be constant, so that no offsetoccurs.

Tenth Embodiment

FIG. 22 is a circuit diagram showing the configuration of a PLL circuitaccording to the tenth embodiment of the present invention. In FIG. 22,this PLL circuit is different from the PLL circuit in FIG. 1 in thatcharge pump circuit 2 is replaced by a charge pump circuit 113.

Charge pump circuit 113 is different from charge pump circuit 2 in that,in place of power-supply potential VCC and ground potential GND, outputpotentials V3, V4 of variable voltage sources 114, 115 are applied,respectively, to the sources of MOS transistors 3, 6. Variable voltagesources 114, 115 are controlled by control circuits 7, 8, respectively.Variable voltage source 114 and P-channel MOS transistor 3 constitute avariable current source 113 a, and variable voltage source 115 andN-channel MOS transistor 6 constitute a variable current source 113 b.

Variable voltage source 114 performs fine adjustment of source potentialV3 of P-channel MOS transistor 3 so as to maintain current Ic flowingthrough P-channel MOS transistor 3 at conduction of switching element 4to be at a constant value, irrespective of control potential VC.Variable voltage source 115 performs fine adjustment of source potentialV4 of N-channel MOS transistor 6 so as to maintain current Id flowingthrough N-channel MOS transistor 6 at conduction of switching element 5to be at a constant value, irrespective of control potential VC.Therefore, current Ic, Id can be maintained at a constant value moreprecisely than the case with the PLL circuit in FIG. 1, so thatoccurrence of an offset can reliably be prevented.

It is noted that, though, P-channel MOS transistor 3 and N-channel MOStransistor 6 constitute variable current sources 2 a, 2 b, respectively,in the first embodiment, and variable voltage source 111 and P-channelMOS transistor 3, and variable voltage source 112 and N-channel MOStransistor 6 constitute variable current sources 110 a, 110 b,respectively, in the ninth embodiment, and further, current voltagesource 114 and P-channel MOS transistor 3, and variable voltage source115 and N-channel MOS transistor 6 constitute variable current sources113 a, 113 b, respectively, in the tenth embodiment, the variablecurrent source is not limited thereto, and may have any configuration inwhich output current can be controlled.

The embodiments disclosed herein should be considered in all terms asillustrative, not limitative. The scope of the present invention isdefined only by the attached claims, not by the description above, andis intended to encompass all modifications within the meaning and scopeof the claims and equivalents.

What is claimed is:
 1. A clock synchronizer generating a second clocksignal synchronized with a first clock signal, comprising: a phasedifference detection circuit for detecting a phase difference betweensaid first and second clock signals, and setting a first control signalto be at an activated level for a time period corresponding to the phasedifference; a loop filter connected to a predetermined node; acurrent-supply circuit for supplying current to said loop filter inresponse to the first control signal from said phase differencedetection circuit; and a clock generating circuit for generating saidsecond clock signal in accordance with a potential of said predeterminednode; wherein said current-supply circuit includes a variable currentsource whose output current can be controlled, a first switching circuitfor passing output current of said variable current source through saidloop filter in response to that said first control signal is set to beat the activated level, and a first control circuit for controlling saidvariable current source such that predetermined constant current flowsfrom said variable current source to said loop filter, based on thepotential of said predetermined node, wherein: said variable currentsource includes a first transistor of a first conductivity type whoseinput electrode receives a first control potential, said first switchingcircuit connects said first transistor between a line of a firstpower-supply potential and said loop filter in response to that saidfirst control signal is set to be at the activated level, and said firstcontrol circuit controls said first control potential such thatpredetermined constant current flows through said first transistorconnected between the line of said first power-supply potential and saidloop filter, based on the potential of said predetermined node, saidfirst control circuit including  a second transistor of a firstconductivity type, whose first electrode is connected to the line ofsaid first power-supply potential, and whose input electrode isconnected to a second electrode of said second transistor, foroutputting said first control potential from the second electrode,  athird transistor of a second conductivity type whose first electrode isconnected to the second electrode of said second transistor and whoseinput electrode receives the potential of said predetermined node, and a first resistance element connected between a second electrode of saidthird transistor and a line of a second power-supply potential.
 2. Theclock synchronizer according to claim 1, wherein said first controlcircuit further includes a second resistance element connected betweenthe second electrode of said second transistor and the line of saidsecond power-supply potential.
 3. The clock synchronizer according toclaims 1, wherein said variable current source further includes a fourthtransistor of a first conductivity type, connected in parallel with saidfirst transistor, whose input electrode receives a constant biaspotential.
 4. The clock synchronizer according to claim 1, furthercomprising: a lock detection circuit for detecting whether or not thephase difference between said first and second clock signals is smallerthan a predetermined level, setting a lock detection signal to be at anactivated level when it is smaller, and setting said lock detectionsignal to be at an inactivated level when it is larger, said variablecurrent source further including a fourth transistor of a firstconductivity type whose input electrode receives a constant biaspotential, said first switching circuit connecting said first transistorbetween the line of said first power-supply potential and said loopfilter when said lock detection signal is at an activated level, andconnecting said fourth transistor between the line of said firstpower-supply potential and said loop filter when said lock detectionsignal is at an inactivated level, in response to that said firstcontrol signal is set to be at an activated level.
 5. The clocksynchronizer according to claim 1, further comprising: a lock detectioncircuit for detecting whether or not the phase difference between saidfirst and second clock signals is smaller than a predetermined level,setting a lock detection signal to be at an activated level when it issmaller, and setting said lock detection signal to be at an inactivatedlevel when it is larger, said variable current source further includinga fourth transistor of a first conductivity type whose input electrodereceives a second control potential, said first switching circuitconnecting said first transistor between the line of said firstpower-supply potential and said loop filter when said lock detectionsignal is at an activated level, and connecting said fourth transistorbetween the line of said first power-supply potential and said loopfilter when said lock detection signal is at an inactivated level, inresponse to that said first control signal is set to be at an activatedlevel, said current-supply circuit further including a second controlcircuit for controlling said second control potential such that currentflowing through said fourth transistor connected between the line ofsaid first power-supply potential and said loop filter is increased inaccordance with a potential difference between said first power-supplypotential and a potential of said predetermined node, based on thepotential of said predetermined node.
 6. The clock synchronizeraccording to claim 1, wherein said first control signal is a signal foradvancing a phase of said second clock signal: said phase differencedetection circuit sets said first control signal to be at an activatedlevel for a time period corresponding to a phase difference between saidfirst and second clock signals when the phase of said second clocksignal is delayed with respect to said first clock signal, sets a secondcontrol signal for delaying the phase of said second clock signal to beat an activated level for a time period corresponding to a phasedifference between said first and second clock signals when the phase ofsaid second clock signal is advanced with respect to said first clocksignal, and sets said first and second control signals to be at anactivated level for a predetermined period of time when phases of saidfirst and second clock signals agree with each other; and saidcurrent-supply circuit supplies current of a first polarity to said loopfilter in response to that said first control signal is set to be at anactivated level, and also supplies current of a second polarity to saidloop filter in response to that said second control signal is set to beat an activated level.
 7. The clock synchronizer according to claim 6,wherein said variable current source further includes a fourthtransistor of a second conductivity type whose input electrode receivesa second control potential; and said current-supply circuit includes asecond switching circuit for connecting said fourth transistor betweensaid loop filter and the line of said second power-supply potential inresponse to that said second control signal is set to be at an activatedlevel, and a second control circuit for controlling said second controlpotential such that said predetermined constant current flows throughsaid second transistor connected between said loop filter and the lineof said second power-supply potential, based on a potential of saidpredetermined node.
 8. The clock synchronizer according to claim 7,further comprising a precharge circuit for precharging saidpredetermined node to be at a predetermined potential in response toapplication of said first and second power-supply potentials.
 9. Theclock synchronizer according to claim 6, wherein said current-supplycircuit further includes a fourth transistor of a second conductivitytype whose input electrode receives a constant bias potential, and asecond switching circuit connecting said fourth transistor between saidloop filter and the line of said second power-supply potential inresponse to that said second control signal is set to be at an activatedlevel.
 10. The clock synchronizer according to claim 9, furthercomprising a precharge circuit for precharging said predetermined nodeto be at said first power-supply potential in response to application ofsaid first and second power-supply potentials.
 11. The clocksynchronizer according to claim 1, wherein said first control signal isa signal for delaying the phase of said second clock signal, said phasedifference detection circuit sets said first control signal to be at anactivated level for a time period corresponding to a phase differencebetween said first and second clock signals when the phase of saidsecond clock signal is advanced with respect to said first clock signal,sets a second control signal for advancing the phase of said secondclock signal to be at an activated level for a time period correspondingto a phase difference between said first and second clock signals whenthe phase of said second clock signal is delayed with respect to saidfirst clock signal, and sets said first and second control signals to beat an activated level for a predetermined period of time when the phasesof said first and second clock signals agree with each other, and saidcurrent-supply circuit supplies current of a first polarity to said loopfilter in response to that said first control signal is set to be at anactivated level, and also supplies current of a second polarity to saidloop filter in response to that said second control signal is set to beat an activated level.
 12. The clock synchronizer according to claim 11,wherein said current-supply circuit further includes a fourth transistorof a second conductivity type whose input electrode receives a constantbias potential, and a second switching circuit for connecting saidsecond transistor between said loop filter and the line of said secondpower-supply potential, in response to that said second control signalis set to be at an activated level.
 13. The clock synchronizer accordingto claim 12, further comprising a precharge circuit for precharging saidpredetermined node to be at said first power-supply potential inresponse to application of said first and second power-supplypotentials.
 14. The clock synchronizer according to claim 1, whereinsaid variable current source further includes a variable potentialsource for outputting said first power-supply potential, the potentialof which can be controlled; and said first control circuit furthercontrols said variable potential source such that predetermined constantcurrent flows through said first transistor connected between the outputnode of said variable potential source and said loop filter, based on apotential of said predetermined node.
 15. The clock synchronizeraccording to claim 1, wherein said loop filter includes a resistanceelement and a capacitor connected in series between said predeterminednode and a line of a reference potential.
 16. A clock synchronizergenerating a second clock signal synchronized with a first clock signal,comprising: a phase difference detection circuit for detecting a phasedifference between said first and second clock signals, and setting acontrol signal to be at an activated level for a time periodcorresponding to the phase difference; a loop filter including aresistance element and a capacitor connected in series between apredetermined node and a line of a reference potential; a current-supplycircuit for supplying current to said loop filter in response to saidcontrol signal from said phase difference detection circuit; and a clockgenerating circuit for generating said second clock signal in accordancewith a potential of said predetermined node; said current-supply circuitincluding a first transistor whose input electrode receives a controlpotential, a switching circuit for connecting said first transistorbetween a line of a first power-supply potential and said loop filter,in response to that said control signal is set to be at an activatedlevel, and a control circuit for controlling said control potential suchthat predetermined constant current flows through said first transistorconnected between the line of said first power-supply potential and saidloop filter, based on a potential of a node between said resistanceelement and said capacitor; and said control circuit including a secondtransistor of a first conductivity type, whose first electrode isconnected to the line of said first power-supply potential, and whoseinput electrode is connected to a second electrode of said secondtransistor, for outputting said control potential from the secondelectrode, a third transistor of a second conductivity type whose firstelectrode is connected to the second electrode of said second transistorand whose input electrode receives the potential of said node betweensaid resistance element and said capacitor, and a first resistanceelement connected between a second electrode of said third transistorand a line of a second power-supply potential.